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The ARM Cortex-A53 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A53 is an superscalar processor capable of dual-issuing some instructions.〔(【引用サイトリンク】 title=Cortex-A53 Processor )〕 It is available as SIP core to licensees, and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration. ==Overview== * 8-stage pipelined processor with 2-way superscalar execution pipeline * DSP and NEON SIMD extensions are mandatory per core * VFPv4 Floating Point Unit onboard (per core) * Hardware virtualization support * TrustZone security extensions * 64-bit cache lines * 10-entry L1 TLB, and 512-entry L2 TLB * 4 Kb conditional branch predictor, 256-entry indirect branch predictor 抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)』 ■ウィキペディアで「ARM Cortex-A53」の詳細全文を読む スポンサード リンク
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